Mentor, a Siemens business, has recently announced that SGS-TüV Saar, an independent compliance company, has granted ISO 26262 compliance certification for the tool validation report of key software elements in Mentor’s new Veloce® Strato™ hardware accelerated simulation platform. This certification highlights Mentor's strong commitment to functional safety and its leadership in hardware acceleration technology, helping chip designers meet and exceed the rising safety and quality standards in the global automotive industry.
This marks the 22nd time that Mentor has successfully achieved ISO 26262 product certification. The latest features in the Mentor Safe programs reflect the company’s ongoing effort to ensure that all flagship products in its leading portfolio of electronic design solutions pass rigorous functional safety verification. These programs are essential for meeting the evolving demands of the automotive sector.
Eric Selosse, Vice President and General Manager of Mentor Hardware Acceleration Simulation, emphasized: “As the demand for autonomous driving and advanced ADAS systems continues to reshape the automotive industry, leading manufacturers and their suppliers are increasingly looking for pre-certified design automation tools and documentation. This helps reduce time-to-market while ensuring optimal cost-effectiveness. To meet this growing need, Mentor has introduced platforms and solutions that simplify the development of automotive-grade ICs with the help of the Mentor Safe ISO 26262 validator.â€
The Software Tools Validation Report from Mentor provides comprehensive documentation, including hypothetical use cases and evidence, demonstrating that the Validation Software Tool is suitable for any Tool Confidence Level (TCL) activity or ISO 26262-required tasks. SGS-TüV Saar has certified the following software components of the Veloce Strato platform:
- **Veloce Strato OS**: A powerful system-level verification platform that utilizes advanced techniques for high-quality RTL and GL hardware descriptions. It allows users to manage the entire verification process, track progress metrics, and use advanced stimuli to quickly reach coverage goals. The OS supports compilation and emulation of composable hardware models written in VHDL, Verilog, and SystemVerilog, as well as non-integratable test environments in multiple languages like C, C++, and SystemC.
- **Veloce Fault App**: Enables users to inject faults into the design to simulate real-world environmental events that could lead to circuit failures. This app helps customers identify and address potential security vulnerabilities early in the design process.
- **Veloce Coverage App**: Provides detailed statistics on assertion coverage, feature coverage, and code coverage during hardware accelerated emulation, giving users deeper insights into their design’s reliability.
- **Veloce DFT App**: Speeds up the verification of testable designs by fully validating test vectors and DFT logic before chip production, reducing risk and accelerating the chip turn-on process.
With these tools, Mentor continues to support the automotive industry in achieving higher levels of safety, efficiency, and reliability in semiconductor design.
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