Mentor, a Siemens business, has announced that SGS-TüV Saar, an independent compliance company, has granted ISO 26262 compliance certification for the tool validation report of key software elements in Mentor’s new Veloce® Strato™ hardware accelerated simulation platform. This certification reinforces Mentor's leadership in functional safety and hardware acceleration technology, empowering chip designers to meet and exceed the growing demands of the global automotive industry for safety and quality.
This marks the 22nd time that Mentor has successfully achieved ISO 26262 product certification. The latest updates to the Mentor Safe programs reflect the company’s ongoing commitment to ensuring that all its flagship products within its leading portfolio of electronic design solutions pass rigorous functional safety verification. This effort is aimed at supporting the development of safe and reliable systems across industries.
Eric Selosse, Vice President and General Manager of Mentor Hardware Acceleration Simulation, stated, “The demand for autonomous driving and advanced ADAS systems continues to reshape the automotive landscape. Leading automakers and their suppliers are increasingly looking for pre-certified design automation technologies and documentation to shorten time-to-market and ensure cost-effective solutions.†He added, “To meet these needs, Mentor has introduced platforms and solutions that simplify the development of automotive-grade ICs through the use of the Mentor Safe ISO 26262 validator.â€
The Software Tools Validation Report from Mentor provides comprehensive documentation that includes hypothetical use cases and evidence demonstrating that the Validation Software Tool is suitable for any Tool Confidence Level (TCL) activity or tasks required by ISO 26262. SGS-TüV Saar has certified the following software components of the Veloce Strato platform:
- **Veloce Strato OS** offers advanced techniques for high-quality system-level, RTL, and GL hardware verification. It allows users to manage the entire verification process, track progress metrics, and utilize advanced stimulus methods to achieve coverage goals efficiently. The OS supports compiling and emulating composable hardware models written in VHDL, Verilog, and SystemVerilog, as well as non-integratable test environments in multiple languages such as C, C++, and SystemC.
- **Veloce Fault App** enables users to inject faults into designs to simulate real-world environmental events that could lead to system failure. This helps identify and address potential security vulnerabilities before they become issues.
- **Veloce Coverage App** allows users to collect detailed statistics on assertion coverage, feature coverage, and code coverage during hardware accelerated emulation, enhancing the depth of analysis.
- **Veloce DFT App** streamlines the verification of testable designs by validating test vectors and DFT logic prior to chip production, improving confidence, reducing risk, and minimizing the time needed for chip bring-up.
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