Design of GPS-2000 Digital Newspaper Clock

0 Preface

The speed of digital technology is amazing. It has penetrated into every corner of radio and television. However, for an electronic clock, it is indispensable for the broadcast department. We combine advanced working conditions with advanced electronic devices such as:

1. The one-chip computer adopts AT89C52 which is extremely strong in anti-interference.

2. The clock chip selects X1228, because the main feature of X1228 is that there are 6 analog trimming bits inside to adjust the on-chip load capacitance between X1 and X2 pins. The effective load capacitance ranges from 5pf to 19.75pf. There are different weights, which will allow the use of 6pf or 12.5pf crystals, which makes the internal clock more accurate.

3. Using the high-precision UTC (World Time) in the GSU-36A3 (GPS) receiving module, we have designed and developed this precise time electronic clock. There are two ways to display it: (1) LED digital display, its driver chip has 8 drivers, each driver outputs a maximum current of 50mA. (2) LCD liquid crystal display.

First, capture high quality GPS information

The GPS-2000 digital alarm clock is a GSU-36A3 (GPS) receiver module with 18 hybrid channel receiving systems. The system output is a serial output with a level of RS-232 interface. The antenna part of GSU-36A3 is an active antenna. It does not support passive antennas. Therefore, the length of the antenna is very strict. The antenna is a 50-ohm copper-axis cable. In the GPS sensor, we only use 5 GPSs in this system. sensor.

(1) GPS positioning data sensor (GPGGA)

This sensor is used to receive the GPS quality indication. When the received data is 0, the system corrects the real-time clock system to be invalid.

(2) GPS satellite signal sensor (GPGSU)

The total number of satellites that may be received within the current field of view. When the system receives less than 4 GPS satellites, the system corrects the real-time clock system.

(3) GPS sleep working mode setting information sensor (PKODG)

When receiving the wireless status disconnection = 1, when short circuit = 2, the correction to the real-time clock system is invalid.

(4) Longitude/latitude sensor (GPGLL)

This system corrects the real-time clock when there is a change in the east.

(5) GPS time and date sensor (GPZDA)

When the current 4 sensors are working properly, the time received by this sensor can be used to correct the real-time clock system. The circuit diagram is shown in Figure 1.

Circuit diagram

Second, the anti-jamming design of GPS-2000 digital newspaper clock

We know that most of the interference comes from the common part, in order to make the MCU part of the system safe and reliable to execute the command: (1) Power part We use 5S5-200 (DC-DC) power isolation module. (2) The watchdog circuit is added by applying the MAX813 chip. (3) The input and output data must also be isolated. We use high-speed photocouple 6N137 as the isolation device. There are 5 data output lines, 1 serial input line, and 4 output control lines. The above 10 lines have been isolated.

Third, the design of the timekeeping circuit

1 Clock chip X1228 uses an external 32.768KHZ quartz crystal to maintain accurate year, month, day, week, hour, minute, and second. The real-time clock has leap year corrections and century bytes, and the clock can be corrected for months less than 31 days.

2 Using a 14-bit binary serial counter/divider CD4060 (with internal oscillator) to form an oscillation frequency of 3.2768MHZ, divide the frequency by 1600HZ, and then divide the CD4024 by a 7-bit binary serial counter to get 800HZ. The two frequencies pass through the CD4066 four-way analog switch under the control of the central processor through an amplifying circuit, an impedance matching circuit, and finally balance the output OdB signal.

Fourth, the design of the display circuit

Because there is no week in the GPS, then we are divided into two parts when sending the display:

(1) We have taken the data of year, month, day and week as x1228 internal data;

(2) GPS data is used for hours, minutes and seconds. When the GPS information is not received, the x1228 internal time, minute and second data are sent. The digital driver chip uses the 6B595, and the LCD display uses the 16&TImes; 2 display module.

Fifth, the design of the interface circuit

The GPS output is a serial output, but it is not a TTL level, but an RS-232 level. The RS-232 level transmission cannot exceed 20 meters, so it must be transmitted using the RS-485 interface circuit when transmitting over long distances. . RS-485 has multi-point two-way communication capability. The transceiver adopts balanced transmission and differential reception. The communication distance is several tens of meters to several kilometers. The transmission of digital signals increases with distance and the signal transmission rate increases. Reflection, crosstalk, attenuation, and common ground noise will cause signal distortion, which limits the communication distance. The ordinary TTL circuit has poor input capability, low input resistance, low sensitivity, and poor anti-interference ability. Short, RS-232 interface circuit, the output signal swing of the driver is much larger than the TTL level, which greatly improves the anti-interference ability. However, the RS-232 standard specifies that the driver allows a capacitive load of 2500 PF, and the communication distance will be affected by this capacitor. Restrictions, for example, when using a 150 PF/m communication cable, the maximum distance is 15 m. Another reason for the short RS-232 transmission distance is that RS-232 is a single-ended signal transmission, which has common ground noise and cannot suppress common mode interference. The GPS-2000 digital alarm clock has 10 signal timing output terminals, 1 RS-485 signal input terminal and 18 RS-485 signal output terminals. The output terminal is to provide GPS signal and calibration microcomputer to the subclock, or computer network. The clock makes the clock display and the microcomputer automatically broadcast to full synchronization.

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